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Honored Contributor
Honored ContributorHPS CLK1 and CLK2 crystal oscillators
In most eval boards of Cyclone 5 Soc I have seen, they generate the 25 MHz HPS_CLK1 and HPS_CLK2 from a chip that has one input clk pin and multiple output clock pins. Some of the chip outputs are cl...
Altera_ForumHonored Contributor
Honored ContributorI believe you can but there is a jitter requirement for the HPS PLL Input (refer to https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_51002.pdf page 53). Also note that some peripheral (USB, Ethernet) may require you to supply an external clock of certain frequency to the PHY or the SoC chip (depending on mode).
