How to write a 88bit*4096 ram in VHDL?

Quartus can be a bit tempremental in infering rams if you dont follow their coding guidlines properly. I have previously had problems (pre Q9, seems ok now) with some rams not being infered if there is no write-enable (some would work, some would not), and the response I got back was that "there is no write enable, so you're not following the coding guidelines).

With the OP could, I agree it should work, but I get the feeling it has built an asynchronous read mux in-front of the output register because of the if/else condition. It is always safer to completly separate your read and write logic, the way FvM suggested.