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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to write a 88bit*4096 ram in VHDL?

Hi everyone, I am trying to write a 88bit*4096 RAM all in VHDL. I defined an array as RAM and use package to initialize it. But there is an error when I compile it saying that *Erro...
Altera_Forum's avatar
Altera_Forum
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14 years ago

The original warning message is preceeded by this important line

--- Quote Start ---

Info: RAM logic "ram1" is uninferred due to asynchronous read logic

--- Quote End ---

In my opinion, the analysis is incorrect. Quartus apparently doesn't like the nested if control signals. Try with this logically equivalent construct: 

   if cs = '0' and oe = '0' then
      data_o <= ram1(conv_integer(addr));
   end if;
   if cs = '0'  and oe = '1' then
      ram1(conv_integer(addr)) <= data_i;
   end if;