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Altera_Forum
Honored Contributor
Honored Contributorhow to use another vhdl file's function?
bin2bcd7 is not in the scope and error at H1:bin2bcd7 port map (X"0001" => bin_in, bcd7_out => HEX0); bin2bcd7.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_...
Altera_ForumHonored Contributor
Honored ContributorYou will learn soon that "less error" doesn't always mean better ;)
It should work without the 'X', but from what I see your component declaration in the architecture is wrong, you have defined bin_in and bcd7_out as std_logic signals instead of std_logic_vector.
