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Altera_Forum
Honored Contributor
Honored Contributorhow to use a fixed portion of fpga except logic lock?
I am working at module level and my cells seem to be scattered over the fpga board and hence i am experiencing high IC delays and if i constrain one the other paths get affected... I know about og...
Altera_ForumHonored Contributor
Honored Contributorohh thanks kevin...i implemented your ideas and am seeing some meaningful results..
However i am not constraining the reset signal with and input delay constraint and it is being reported as an unconstrained path as obvious.. What i learnt was to treat reset signals not as other input signals but i am still not able to constraint is as i really dont have the clear idea to contraint a reset signal?
