Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

how to use a fixed portion of fpga except logic lock?

I am working at module level and my cells seem to be scattered over the fpga board and hence i am experiencing high IC delays and if i constrain one the other paths get affected... I know about og...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

ohh thanks kevin...i implemented your ideas and am seeing some meaningful results..

However i am not constraining the reset signal with and input delay constraint and it is being reported as an unconstrained path as obvious..

What i learnt was to treat reset signals not as other input signals but i am still not able to constraint is as i really dont have the clear idea to contraint a reset signal?