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Altera_Forum's avatar
Altera_Forum
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14 years ago

how to use a fixed portion of fpga except logic lock?

I am working at module level and my cells seem to be scattered over the fpga board and hence i am experiencing high IC delays and if i constrain one the other paths get affected... I know about og...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Can you throw some more light on the constraint with the input to output pin propagation delay?