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FvM you said:
"The simplest way to do the result scaling and saturation is to use IEEE fixed point package."
Are you talking about the fixed_pkg? Is it synthesizeable? How exactly does it help here? I mean if I am going to use a multiplier IP block from the IP catalog to do multiplication, the top level ports of it are std_logic_vector. So how would the fixed_pkg help in that?
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Yes it is synthesisable, if you download the '93 compatible version (for Quartus 15 and earlier)or it is built in with q15.1 prime pro.
It allows you declare fixed point numbers in VHDL like this:
signal my_fixed : sfixed(1 downto -14); -- 2 integer bits, 14 fraction bits
The only advantage this gives you is that it easier to understand from the VHDL. The synthesised hardware will be identical to using numeric_std or instantiating the lpm_mult.
It has conversion functions to std_logic_vector if you need to connect to the lpm_mult, or you can simply just write:
my_new_fixed <= my_fixed * my_fixed2;
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