Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to solve this warning
hello,everyone, Here are several Warnings of my design, I list below, and how to avoid these warnings? 1- --- Quote Start --- Warning: (10273) Verilog HDL warning at FLM_CTL.v(100): ext...
Altera_ForumHonored Contributor
Honored ContributorOne way to not use latch, but use DFF in order to keep a signal is that to use the ENABLE input of the DFF.
You should manage a logic that move your enable at the istant you wanna "latch" your data. Of course your input signal shall be sampled at the same clk of the DFF you wanna use.
