Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to solve this warning
hello,everyone, Here are several Warnings of my design, I list below, and how to avoid these warnings? 1- --- Quote Start --- Warning: (10273) Verilog HDL warning at FLM_CTL.v(100): ext...
Altera_ForumHonored Contributor
Honored Contributorand always this warning:Warning:
--- Quote Start --- Verilog HDL Always Construct warning at RGBDisplay.v(482): variable "PRE_FLM_READ_DATA1" may not be assigned a new value in every possible path through the Always Construct. Variable "PRE_FLM_READ_DATA1" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design. --- Quote End --- what should i do?
