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Altera_Forum
Honored Contributor
18 years agoHow to solve this warning
hello,everyone, Here are several Warnings of my design, I list below, and how to avoid these warnings? 1- --- Quote Start --- Warning: (10273) Verilog HDL warning at FLM_CTL.v(100): ext...
Altera_Forum
Honored Contributor
18 years ago --- Quote Start --- Hi, How about using {16{1'bz}} or 16'bzzzzzzzzzzzzzzzz instead of 16'bz? For the second warning, altera doesn't recommend to use latches. You really need one? Thanks --- Quote End --- i need to keep the value .if not use the latch, what can instead? thank you