Forum Discussion
Altera_Forum
Honored Contributor
14 years agoYou will need a simple bit generator based on cyclic shift register as Tricky suggested:
-- not tested
process(reset,clk)
begin
if reset = '1' then
shift_reg <= x"0123456789ABCDEF"; -- 64 bits initial value
elsif rising_edge(clk) then
shift_reg <= shift_reg(62 downto 0) & shift_reg(63);
end if;
end process;i.e. reg started with initial value then on first clock edge it shifts with bit 63 assigned to bit 0, 0 to 1 ...62 to 63 and so on your data is then assign any one or more bits of shift_reg as per data width.