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Honored Contributor
Honored ContributorHow to route output clock of alt2gxb to a pll?
Hi, The error information is "Error: Clock input port inclk[0] of PLL "pllo:u_pllo|altpll:altpll_component|pll" must be driven by a non-inverted input pin or another PLL, optionally through a Cl...
Altera_ForumHonored Contributor
Honored ContributorHi,
I don't know if it meets your requirement, but the only way I can figure out is to use phase comp fifo in the gxb like handbook vol-2 page 2-131. I attached the sample. Thanks!
