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Honored Contributor
Honored ContributorHow to route output clock of alt2gxb to a pll?
Hi, The error information is "Error: Clock input port inclk[0] of PLL "pllo:u_pllo|altpll:altpll_component|pll" must be driven by a non-inverted input pin or another PLL, optionally through a Cl...
Altera_ForumHonored Contributor
Honored ContributorHello,
The siigx handbook says, in the volume-2 page 7-73, "An internally generated global signal cannot drive the PLL". The clock output from the alt2gxb is always routed through global signal, so you can't do this.
