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Honored Contributor
Honored ContributorHow to reset a ram?
Hi, in my vhdl design I got a ram signal R then I try to test it against A with "if A > R then..." but R starts with a 'X' value so the test is not working. What could I do to solve that problem? ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- To reset the RAM in modelsim to get rid of x you could use the mem load command: mem load -filltype value -filldata 0 -fillradix symbolic /tb/the_ram_to_be_resetted/altsyncram_component/m_default/altsyncram_inst/mem_data or emulate random data: mem load -filltype rand -filldata 0 -fillradix symbolic /tb/the_ram_to_be_resetted/altsyncram_component/m_default/altsyncram_inst/mem_data In a real design you need a memory initialization file. If not supplied or not found Quartus sets all initial values to 0. This behaviour is may depending on the type of FPGA. --- Quote End --- The code the OP has posted indicates the ram is already initialised to 0. The Xs are likely the results of code problems elsewhere.
