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Honored Contributor
Honored ContributorHow to reset a ram?
Hi, in my vhdl design I got a ram signal R then I try to test it against A with "if A > R then..." but R starts with a 'X' value so the test is not working. What could I do to solve that problem? ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- How to tell my vhdl design to ignore X? --- Quote End --- If you do that, you're likely to break the design on the FPGA. Basically, fix your testbench so that something is written to the ram before you start, or give the ram an initial startup value via a .mif file. Or you could infer the ram and set the initial contents with a function.
