How to reset a ram?

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Hi,

in my vhdl design I got a ram signal R then I try to test it against A with "if A > R then..." but R starts with a 'X' value so the test is not working. What could I do to solve that problem?

Thanks.

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for power up conditions look at section 3-14:

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ram_rom.pdf

for reset, you can only reset output ram registers if available