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Altera_Forum's avatar
Altera_Forum
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9 years ago

how to remove warning(11106) Warning (11106): Shared VREF is used as GPIO ().

Hello All,

For one of our older FPGA i am planning to add some interface. but before that i have selected an fpga from arria 10 family, while the total no of gpio i need is 270 and fpga family that i selected has more than 350. At first a compiled it with the new family from arria 10 without any gpio assignment so that the tool can do that on its own. but when i checked the fitter report i got a warning saying(got 6 warning like that)

"Warning (11106): Shared VREF Y6 is used as GPIO (pin SFP_txdis[0]). This action reduces fMAX performance of this pin."

Further when i checked in pin planner i found that the tool is applying three pins to vref pin while the fpga had many pins that are left free.

Searched web but couldnot find any solution. Please tell if there is any setting so that default pin assignment does not put up pins at vref pin area

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hi,

    I doubt that this is what you want to hear, but please assign the pins manually. I mean, what's the point? You've got to develop and manufacture a PCB eventually, then fixed pin assignments are mandatory anyway (imagine you re-synthesize your design and the pins don't match your PCB any more!).

    I assume you just wanted to quickly synthesize your preliminary design to see if it fits into the FPGA. That's fine without pin assignments. Even though no one can guarantee the same performance once you've assigned the pins. But then just ignore that warning, and resolve it when you assign the pins.

    Also, keep in mind your FPGA only has so many I/O banks. If you need different I/O standards (e.g. some with 3.3V, some with 2.5V, etc.), I strongly recommend to settle on some pin assignments in an early stage. Otherwise you might be surprised that you'll run our of pins (in one of my designs I also had plenty of excess pins, but only very few of them were 2.5V while the others were 3.3V and 1.8V, wasting almost around 40 unusable 2.5V-pins).

    Best regards,

    GooGooCluster
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    hii GooGooCluster,

    Yes you are right i just wanted to check whether it fits or not to the new design. Manual assignment or via tcl script is my final way of doing . Also thanks for your second suggestion as i have faced the same issue but resolved it with some research. I will keep in mind all the points that u have suggested. thanks again..........