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Altera_Forum
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14 years ago

How to reduce the area of my design?

Hi all, I'm doing an FPGA design with Stratix 3; And our design doesn't fit into a single chip. Our FPGA has 38000 Combinational ALUTs and 38000 dedicated logic registers; Our design tak...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

I agree with ELI_HAIT. You must share your ressources into your system in order to use less logic elements. If you use lot of shift registers, try to use the RAM (you can generate it with MegaWizard) and that would decrease your LE numbers (and Quartus will use the FPGA memory bits to make that).

And if you can share your ressources, try to use FSM to coordinate your system.