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Altera_Forum
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14 years ago

How to reduce the area of my design?

Hi all, I'm doing an FPGA design with Stratix 3; And our design doesn't fit into a single chip. Our FPGA has 38000 Combinational ALUTs and 38000 dedicated logic registers; Our design tak...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

if your design is so much exceed your FPGA, i don't think that different compilation guidelines would solve the problem.

I think that you should think creatively about logical reduction, i.e. if you have few instances of the same module, maybe you can create single module which operates in time sharing? or use the FPGA memory as ROM tables instead of complex logic?