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Altera_Forum
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14 years ago

How to reduce the area of my design?

Hi all, I'm doing an FPGA design with Stratix 3; And our design doesn't fit into a single chip. Our FPGA has 38000 Combinational ALUTs and 38000 dedicated logic registers; Our design tak...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I would go through the fit report and see which entities are using the most logic - and then see if you could afford to change their size.