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Altera_Forum
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15 years ago

How to reduce the area of my design?

Hi all, I'm doing an FPGA design with Stratix 3; And our design doesn't fit into a single chip. Our FPGA has 38000 Combinational ALUTs and 38000 dedicated logic registers; Our design tak...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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And another question here:

the report shows that the logic utilization is 55100/38000 （145%）

How is it possible to reach 30% if my Combinational ALUTs utilization is 105% and my dedicated registers' is only 115%?

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Hi,

are you using shift registers and fifos in your design ?

Kind regards

GPK