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These video doesn't show me how to do boundary scan.
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Me neither. Generating BSDL post configuration files can have a purpose in boundary scan testing, but you still need a dedicated test tool.
That's how I do boundary scan test with TopJTAG probe:
Generate a TopJTAG project by importing the Altera .bsd file and optionally the Quartus .qsf file.
The latter gives me symbolical names for all assigned design pins.
Perform the test with configured FPGA in Sample mode to watch the user program operation.
Or switch to Extest, control pin states to perform specific tests.
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