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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

How to keep logic not being optimized away?

Hi guys:

For some applications, I need insert some logic cells in my design. How to keep these logic?

Another question is anyone know what is the delay range of one logic cell? 4 ns? or other results?!

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    --- Quote Start ---

    Hi so your design is working? I'd like to make delay chain too. Can you share your design? :)

    Thank you,

    Honza

    --- Quote End ---

    You can implement delay-chain by using carry chain resource inside of the FPGA.