Honored Contributor
Honored ContributorWhat will happen if you declare the signal pixel_array : PIXEL_TYPE as you described is that you get 400 vectors with 20 D-flip-flops each in your FPGA (which should result in 8000 DFF in 4000 ALMs, if you are using Stratix II FPGAs).
I must admit I mess up everything about the window and what Jens said about external RAM. If you keep those 8000 DFF within the FPGA, you can assign all of them within the same clock cycle if you want. If you keep them in a 32 bits wide memory, you can access one pixel per clock cycle. If you send them serially to a VGA connector, you must send one pixel per clock cycle. If you think of you design as a hardware solution, and then think of the VHDL code as a way of explaining for the compiler what you think of, your solution will always be synthesizable. Do you want to send this window to a monitor?
