oh yes you are right, I just forgot the second declaration, (it would be right if you have just one Bit per Pixel :) ) What I want to tell you was:
type ROW_TYPE is array (natural range 0 to 19) of std_logic_vector(19 downto 0);
type PIXEL_TYPE is arry (natural range 0 to 19) of ROW_TYPE;
signal pixel_array: PIXEL_TYPE;
With my question about the hardware I meant which FPGA, which sensor, which devkit (or custom hw) you are using?
If you have an 400x400 image (20 bits per pixel) where does it comes from?
You can't store the whole image in internal logic so you have to load the 20x20 window each time you need it. Assuming that you have an external RAM with 32-bit data bus than loading needs 250 clock cycles.
Jens