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Joes19's avatar
Joes19
Icon for New Contributor rankNew Contributor
6 years ago
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How to guarantee stable data when altsyncram and state machine use same clock?

Hi everyone, I'm looking to modify a top level design that uses a relatively simple computation module with some muxing and addition inside. All levels of the design run on a single positive edge cl...
  • ak6dn's avatar
    ak6dn
    6 years ago

    ALTSYNCRAM is a synchronous SRAM block, the output data is registered using the outclock. The input data/address/control is registered using the inclock. Connect inclock and outclock to the same source clock to use it as a fully synchronous SRAM. You then just need to meet setup/hold requirements for all the registers and adhere to maximum clock frequency limits for the device (ie, to guarantee SRAM access time met). These are NOT like discrete ASYNC SRAMs which I believe you are comparing them to.

ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
6 years ago

ALTSYNCRAM is a synchronous SRAM block, the output data is registered using the outclock. The input data/address/control is registered using the inclock. Connect inclock and outclock to the same source clock to use it as a fully synchronous SRAM. You then just need to meet setup/hold requirements for all the registers and adhere to maximum clock frequency limits for the device (ie, to guarantee SRAM access time met). These are NOT like discrete ASYNC SRAMs which I believe you are comparing them to.

Joes19's avatar
Joes19
Icon for New Contributor rankNew Contributor
6 years ago

Thanks! I just went back into the megawizard and toggled the option to register outputs with input clock. I'll give it another try, don't mind the pipelined outputs if it saves me from a complicated memory write procedure.