How to get access to signals in SOPC blocks

This is my one big complaint with Altera. They keep an extremely tight lock on their IP cores whereas other vendors will often provide reference designs. The problem with this is that many of the cores either have bugs or are lacking features and you are simply stuck.

I myself am experiencing a great deal of grief with the 8.0 version of the Video IP. Particularly with the clocked input, deitnerlacer, and mixer. And I can't really do anything about it other than rewrite the cores. The video IP is one area where the source code should be made available as there is no way a one size fits all approach will ever be true with video.

However, here is the solution to your problem ...

Create your clocked output core using the megawizard rather than placing it in SOPC builder. Then create a wrapper around the generated core and create your own custom SOPC component. This will give you access to the reset line however you choose to use it. You could even add an extra register address in the wrapper and control it that way.

Jake