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Honored Contributor
Honored ContributorHow to get 45Mhz clock out?
Hi dears: I am using ArriaGX devices, and the board's clock is 100Mhz which is input to the FPGA. And the system need a 45MHz clock, could you have any method to generate this clock through FPG...
Altera_ForumHonored Contributor
Honored Contributorwe don't play magic Josyb. the given data clocking scheme is an implementation issue. You are referring back to possibilty 2 when data is clocked by 45MHz physical clock which is separate from 100Mhz and so needs crossing.
When you process your given fpga data(say from LUT) on 100Mhz with clken at 45Mhz then this fits possibilty 1. Thus data is already in 100Mhz domain and does not need any crossing but will need upsampling if it has to get rid of that clken rate of 45 and join the 100Mhz rate nicely.
