How to get 45Mhz clock out?

--- Quote Start ---

Coming back to the original start of this: can you humour me and explain, in the upsampling case of a 100 MHz system / DAC clock and a 45 MHz sampling rate, where the 45 MHz sampling rate comes from?

--- Quote End ---

The original post is just saying a system clock is 100MHz, fpga modules need 45MHz clock. There is nothing about the issue of DAC or upsampling.

In this scenario, I am suggesting to look at the possibility of running fpga modules at 100MHz enabled by clken at 45MHz rate. So 45 comes from the post.

With regard to upsampling diversion:

if you are given data at 45Mhz sampling rate then you will be told whether system clock is 45MHz or 100MHz (i.e. whether sampling rate = clock or is less).

1) possibility 1: data on 100MHz clock. If you want to upsample it to 100Mhz rate then you use an interpolation technique to create new samples.

2)possibility 2: data on 45MHz clock then you cross it over to 100MHz using dcfifo idea then interpolate it to 100MHz