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Altera_Forum
Honored Contributor
Honored ContributorHow to enable SDRAM ECC in the Qsys
Hi, How can I enable SDRAM ECC in the Qsys? Best Regards
Altera_ForumHonored Contributor
Honored ContributorIt looks like DE0-Nano-SoC only has 32 DQ pins - thus I think you can't use interface width of 40. You can try using 24 and see if it is working.
