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Honored Contributor
Honored ContributorHow to define a variable and assign a variable
want to define and assign variable, however got error when use variable Error (10500): VHDL syntax error at LabT1.vhd(31) near text "variable"; expecting "end", or "(", or an identifier ("variable"...
Altera_ForumHonored Contributor
Honored Contributorwhich vhdl book is good?
how to fix syntax <<, >> and ~? X"55" is 8bit, how to send 8bit data to 4bit port? i know counter, however, what is address counter? i read verilog example that it use state to determine 8 bit to nibble, but where do this state connect with?
