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Honored Contributor
Honored ContributorHow to define a variable and assign a variable
want to define and assign variable, however got error when use variable Error (10500): VHDL syntax error at LabT1.vhd(31) near text "variable"; expecting "end", or "(", or an identifier ("variable"...
Altera_ForumHonored Contributor
Honored Contributoryour guess is right, i have 4 books, 2 of them are using Verilog, 1 of them only teaching logic math, final 1 of them have examples but not have examples i need
would you mind telling me how to fix it directly as i still do not know the correct syntax
