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Honored Contributor
Honored ContributorHow to define a variable and assign a variable
want to define and assign variable, however got error when use variable Error (10500): VHDL syntax error at LabT1.vhd(31) near text "variable"; expecting "end", or "(", or an identifier ("variable"...
Altera_ForumHonored Contributor
Honored ContributorReviewing some of your posts, I get the impression that you are missing a good VHDL text book.
Various VHDL syntax errors in your text: - double begin in the architecture - declaration of regular variables outside a process or function - variable declaration without a type specification - using Verilog operators and comment syntax in VHDL - broken case construct
