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Altera_Forum
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13 years ago

How to create a programmable clock in RTL(Verilog)

Hello, I'd like to be able to program a clock signal to be used internally for clocking other RTL blocks inside a Stratix FPGA. I have a 500 MHz system clock generated by an internal PLL and wo...
Altera_Forum's avatar
Altera_Forum
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13 years ago

This is simply impossible with a digital clock generator.

Besides the 1 Hz frequency resolution, a jitter specification is necessary to decide about possible solutions. In general, the mentioned parameters demand for an analog PLL with low reference frrequency, not feasible with FPGA built-in PLLs.