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Altera_Forum
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18 years ago

How to control the I/O pins during power up or configration

Hi everyone, I'm working on a project which will use fpga as inteface for emif of TI DSP. I will use cyclone or cyclone II as this inteface chip. But some FPGA's I/O pins should remain Low durin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi, Frank

Thanks for your help.

According to cyclone II's DC Characteristics, the Minimum pullup resistance before and during configuration is 10kΩ (when VCCIO=3.3V) , and the maximum VIL level for Ti DSP is 0.8V. which resistance is proper?

Thanks,

Sonic