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Altera_Forum
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18 years ago

How to control the I/O pins during power up or configration

Hi everyone, I'm working on a project which will use fpga as inteface for emif of TI DSP. I will use cyclone or cyclone II as this inteface chip. But some FPGA's I/O pins should remain Low durin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello,

this can be achieved by a resistor. You have to consider minimum weak pullup resistance from datasheet and maximum VIL level for the input. I recently calculated 2.2k maximum pulldown resistance for a similar problem, 1k should work under all conditions without further calculations.

Regards,

Frank