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RZhen11's avatar
RZhen11
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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How to constrain the transceiver Rx data path?

Dear support, I used to only constrain XCVR with the reference clock and expect the Quartus tool to derive all the generated constraints. Recently I found adding logics to the Rx data path is caus...
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  • Nurina's avatar
    Nurina
    2 years ago

    Hello,


    How about sharing through email?

    I'm dropping you an email, you may send your design through there.


    The reason I am requesting your design is to check if the connection/usage of the IP is correct. From there, we can tell if it is a usage problem or timing constraint problem.


    Regards,

    Nurina


Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello,


How about sharing through email?

I'm dropping you an email, you may send your design through there.


The reason I am requesting your design is to check if the connection/usage of the IP is correct. From there, we can tell if it is a usage problem or timing constraint problem.


Regards,

Nurina


RZhen11's avatar
RZhen11
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi Nurina,

Thanks for the offer, I've resolved the issue by adding immediate register at the XCVR.output.fifo with rx_clk.

The actual design is under Export Control, so I can not share easily.

Please give me your email, I'd be happy to carry on discussion with code snippet and timing reports.

I'll mark "Resolved" here.

Thanks,

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