Forum Discussion
MOliv45
New Contributor
New ContributorHow to constrain inter-clock transfers with very low default relationiship (1 ps)?
=== SHORT INTRO === Due to some questionable architecture decisions in the past, we ended up with a large circuit implemented in three related clock frequencies using timing division multiplexing. T...
RichardT_altera
Super Contributor
Super ContributorNo, it does not make sense to me.
The hold value should not be equal or more than the setup value.
Even though there is no timing violation, I worry that the timing analysis might not be invalid or incorrect.
Check the "Timing Analyzer' > 'Waveform' and check whether the launch and latch clock relationship is correct.
Regards,
Richard Tan
