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Altera_Forum's avatar
Altera_Forum
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10 years ago

How to communicate with I2S block that works at much slower frequency to communicate

I am going to write an I2S block soon (I must write my own), one issue I just realized that I have is that the data output must be synchronized with the MCLK clock sent to the DAC. This master clock ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

There are many tutorials for this. Search for "clock domain crossing". For this, I'd use a pair of FIFOs, one for each direction.

One issue that burned me on my first I2S project, the samples are signed integers. I couldn't figure out why I was getting very low audio levels with my square wave test signal (0x0000-0x1111"