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JoelCaruso's avatar
JoelCaruso
Icon for New Contributor rankNew Contributor
5 years ago

How to address two sperate timing constraints in the Arria 10 IO to drive ADC3224 chip (100MSPS)

1st Quartus cannot fit customers timing constrain condition. *as showcased in file* 2nd, Arria 10 cannot fit the timing internally inside FPGA (from DDIO IP output to registers). We checked the prev...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Do you have any updates?

Thanks.

Best regards,

KhaiY

  • JoelCaruso's avatar
    JoelCaruso
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi KhaiY - didn't see your email direct to me, however this issue was addressed by a FAE and solved. The answer was to use PHY Lite for Parallel Interfaces Intel FPGA IP a free IP. Which would perform at a higher frequency than GPIO.