Honored ContributorIf there are multiple FPGAs on the JTAG chain, altera recommends using JTAG buffer chip on TMS, TCK and TDI pins. I could not find a proper schematic for this.
Anyone can help?
Honored ContributorI don't think you'll find a 'proper' schematic detailing this - there are too many options and variations to cover.
I've attached part of a schematic which did just this with 5 Cyclone IV FPGAs on a very large PCB. For reference only (although it did work). Cheers, AlexHonored ContributorI think you used the voltage supply for the buffer chip as 2.5V.
I created a similar schematic using the buffer chip 74LVC541ADB but it did not correctly work. The voltage supply for the buffer chip was 3V. Please check my thread http://www.alteraforum.com/forum/showthread.php?t=53823
