how should i reset my system

Read some of the papers by Cliff Cummings on reset design:

http://www.sunburst-design.com/papers/

The reset signals should be synchronized on a per clock domain basis. A synchronized reset signal asynchronously asserts, but synchronously deasserts, eg. consider an external reset signal ext_rstN, synchronized to clk_fast and clk_slow, fast_rstN would assert when ext_rstN asserts, but deassert after a rising-edge on clk_fast, and slow_rstN would assert when ext_rstN asserts, but deassert after a rising-edge on slow_clk. This ensures that you do not violate the reset setup/hold timing of registers within your design for deassertion of reset.

If you have an external reset, you could have a 'reset cause' register that defaults to being zero, or say '0000_0001' to indicate hard-reset. The reset signal routed to the reset port of that register would be the hard-reset signal synchronized to the clock used on that register. All other reset sources would be used to reset the rest of the logic, but would not reset your 'reset cause' register.

The other bits in the 'reset cause' register would be 'set' by the assertion of the other reset source, however, those reset sources would first need to be synchronized to the reset cause register clock, i.e., the set pulses generated by these reset sources would occur for one clock of the clock used to clock the reset cause register. The register bits could be cleared by a write to that register. A write-1-to-clear scheme is often useful in registers where some other source sets them. The way you clear the bits in the register is to read it, and then write back the value read. That way the write-1's-to-clear value only contains bits that were set. If another reset occurs around the time of the write, when the system restarts, the new reset cause would still be set (and depending on the timing of the reset, the other sources may be set or clear). The write-1-to-clear scheme is often used in interrupt flags registers.

Cheers,

Dave