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thanks,
I shall be possibly translating this code to VHDL for the clock multiplexer. I wonder why this clock multiplexer given in page 16-4 Figure 16-7 does not exist as a megafunction. Anyway, I have a question,
What does the text here mean? This is taken from the clock_mux.v
// A LUT can glitch when multiple inputs slew
// simultaneously (in theory indepently of the function).
// Insert a hard LCELL to prevent the unrelated clocks
// from appearing on the same LUT.
wire [NUM_CLOCKS-1:0] gated_clks
/* synthesis keep */;
I do not see any "LCELL" or "Synthesis keep" anywhere in the code apart from these comments.
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There is a synthesis keep in the snippet you posted, assigned to the gated_clks. They're using the gated_clks to put the 'AND' operation for each clock into one LUT, and then OR'ing those results in another.
The comment and the descriptive text in the manual are describing that this is being done to avoid out_clk = (clk[0] & ena[0]) | (clk[1] & ena[1]) all ending up in a single LUT.
At least, that is my understanding.
If you want to understand it better, my suggestion would be to just take that block in isolation and examine how it maps to the hardware both with and without the 'synthesis keep' shown.
Honored Contributor
