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Altera_Forum's avatar
Altera_Forum
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14 years ago

[Help on VHDL] FATAL ERROR while loading design

Hi guys, I've just started learning VHDL for a week on my own so i'm still very new to it. I'm doing a practice on implementing a 4-bit parallel-out serial shift register.. My codings can be complied...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

your test bench is a good starting point. It is usually easier to generate the clock in a separate process and concentrate on the other signals in your main test bench process.

What are the differences between what you want and what you get?