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Altera_Forum
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14 years ago

[Help on VHDL] FATAL ERROR while loading design

Hi guys, I've just started learning VHDL for a week on my own so i'm still very new to it. I'm doing a practice on implementing a 4-bit parallel-out serial shift register.. My codings can be complied...
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Altera_Forum
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14 years ago

Hi daixiwen (http://www.alteraforum.com/forum/member.php?u=4443)! Thanks for replying my thread.

I realised i had left out the input length but for my case, i have a 2-bit input (AND gate) and it does not match with the 4-bit output!

Instead i tried forcing my inputs to a LOW but then again i realised, i need to be able to switch my input to a HIGH too. Any idea on what should i do? 

        
        din1: in std_logic_vector:="0" ; 
        din2: in std_logic_vector:="0" ;

This was what i did but i couldn't force it a high when after simulating it! What should i do? :confused: