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Altera_Forum
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15 years ago

[Help on VHDL] FATAL ERROR while loading design

Hi guys, I've just started learning VHDL for a week on my own so i'm still very new to it. I'm doing a practice on implementing a 4-bit parallel-out serial shift register.. My codings can be complied...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Try

din: in std_logic_vector(3 downto 0); -- data in

The error message tells you that your port din doesn't have a defined size. AFAIK unconstrained arrays can't be used on ports.