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Altera_Forum
Honored Contributor
18 years agoHeirarchy Jumping
Can anyone recommend a technique in VHDL or Quartus (generic VHDL is always preferable) for debugging where I could run signals from any part of my heirarchy up to the top level of my design to turn ...
Altera_Forum
Honored Contributor
18 years agoHello,
a very general method would be to connect a debugvar: inout debugtype through the hierarchies. The type should be defined in a package used by all design files, the debugvar can be either a signal or a collection of physical pins in design top. Obviously, each debugvar bit can be driven only from one design location. Regards, Frank