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Altera_Forum
Honored Contributor
Honored ContributorHeirarchy Jumping
Can anyone recommend a technique in VHDL or Quartus (generic VHDL is always preferable) for debugging where I could run signals from any part of my heirarchy up to the top level of my design to turn ...
Altera_ForumHonored Contributor
Honored ContributorIt sounds like you need SignalProbe. The most extensive documentation for it is probably in the Quartus handbook. There are also other debug features documented in the handbook.
