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Altera_Forum
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12 years ago

GXB:tranceiver transmission time issue

Hi dears: I have a board which has two same FPGA. Each FPGA has one transmitter. These two FPGA are configured with same configuration file. I use aonther board which has only one FPGA to recei...
Altera_Forum's avatar
Altera_Forum
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12 years ago

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This is "normal" for GXB signals.

GXB transmitters and receivers serialize and deserialize data. The problem with these shift-registers is that you cannot really start or stop them synchronously at both the source and destination, since they're in different chips, and the bit-streams are at Gbps data rates. The "solution" to get around this lack of synchronization is to introduce a protocol for the data sent over the link. For example, send a known pattern over the link, and align each of the receivers to output parallel words based on that pattern - pseudo-random binary sequences are one method of doing this. Protocols like Gigabit Ethernet use 8/10B and 64/66B encoding and they use special lane synchronizing characters, so that you can align the 8-bit output data on one lane, and they use channel bonding characters so that you can align the data across multiple lanes.

If you control both ends of the serial link, then the easiest solution is to use 8/10B encoding, and then use the frame synchronization controls provided by Altera's IP cores.

Cheers,

Dave

--- Quote End ---

Dear Dave:

Thanks for you quickly reply! Several further questions need your help:

1. Do you mean this issue basicly because of these two lanes are in different chips? Otherwise, how can we implement pcie-x4 in single chip, am i right?

2. I am trying to understand your "solution". I use basic mode, but i enable 8b/10b in megawizard. Is it possible for me to solve this issue without changing current

gxb settings? If this is the case, can you point it to me which is of the "frame synchronization controls"? I don't use any 8b/10b control signals in my previous designs.

3. Why they are diffrent so big, with Max difference of about 10 parallel clcok cycles(for my system it's about 100 ns , 10 100Mhz cycles)? Assume my logic process parallel data with pipelining, there is no difference process timing.

4. Though these 2 GXBs in different chips, still i think the time difference should be a constant value. But according my first post, it act like some ramdom value. Very strange. If this is the case, it seems no way to align them?!

Best Regards

Jerry