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Honored Contributor
Honored ContributorGlobal Variables in VHDL
Hello, I am told that the 2008 VHDL allows one to use global variables. Does anyone have nay example code that would demonstrate this? I am interested in any kind of feedback I can get from th...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I should have added to generic any input that goes anywhere e.g. write data of nios. I am still vague about the concept of global signal despite the excitement. --- Quote End --- Just to clear this up, here is a global signal,
library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
signal global : std_logic;
end package my_pkg;
